AVR CPU Core

AVR CPU Core

Introduction This section discusses the AVR core architecture in general. The main function of the

CPU core is to ensure correct program execution. The CPU must therefore be able to

access memories, perform calculations, control peripherals, and handle interrupts.

Architectural Overview Figure 3. Block Diagram of the AVR MCU Architecture

In order to maximize performance and parallelism, the AVR uses a Harvard architecture

– with separate memories and buses for program and data. Instructions in the program

memory are executed with a single level pipelining. While one instruction is being executed,

the next instruction is pre-fetched from the program memory. This concept

enables instructions to be executed in every clock cycle. The program memory is In-

System Reprogrammable Flash memory.

The fast-access Register File contains 32 x 8-bit general purpose working registers with

a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU)

operation. In a typical ALU operation, two operands are output from the Register File,

the operation is executed, and the result is stored back in the Register File – in one

clock cycle.

Six of the 32 registers can be used as three 16-bit indirect address register pointers for

Data Space addressing – enabling efficient address calculations. One of the these

address pointers can also be used as an address pointer for look up tables in

Flash Program

memory. These added function registers are the 16-bit X-, Y-, and Z-register,

described later in this section.

The ALU supports arithmetic and logic operations between registers or between a constant

and a register. Single register operations can also be executed in the ALU. After

Flash

Program

Memory

Instruction

Register

Instruction

Decoder

Program

Counter

Control Lines

32 x 8

General

Purpose

Registrers

ALU

Status

and Control

I/O Lines

EEPROM

Data Bus 8-bit

Data

SRAM

Direct Addressing

Indirect Addressing

Interrupt

Unit

SPI

Unit

Watchdog

Timer

Analog

Comparator

I/O Module 2

I/O Module1

I/O Module n

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an arithmetic operation, the Status Register is updated to reflect information about the

result of the operation.

Program flow is provided by conditional and unconditional jump and call instructions,

able to directly address the whole address space. Most AVR instructions have a single

16-bit word format. Every program memory address contains a 16- or 32-bit instruction.

Program Flash memory space is divided in two sections, the Boot program section and

the Application Program section. Both sections have dedicated Lock bits for write and

read/write protection. The SPM instruction that writes into the Application Flash memory

section must reside in the Boot Program section.

During interrupts and subroutine calls, the return address Program Counter (PC) is

stored on the Stack. The Stack is effectively allocated in the general data SRAM, and

consequently the Stack size is only limited by the total SRAM size and the usage of the

SRAM. All user programs must initialize the SP in the reset routine (before subroutines

or interrupts are executed). The Stack Pointer SP is read/write accessible in the I/O

space. The data SRAM can easily be accessed through the five different addressing

modes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps.

A flexible interrupt module has its control registers in the I/O space with an additional

global interrupt enable bit in the Status Register. All interrupts have a separate interrupt

vector in the interrupt vector table. The interrupts have priority in accordance with their

interrupt vector position. The lower the interrupt vector address, the higher the priority.

The I/O memory space contains 64 addresses for CPU peripheral functions as Control

Registers, SPI, and other I/O functions. The I/O Memory can be accessed directly, or as

the Data Space locations following those of the Register File, $20 - $5F.

ALU – Arithmetic Logic

Unit

The high-performance AVR ALU operates in direct connection with all the 32 general

purpose working registers. Within a single clock cycle, arithmetic operations between

general purpose registers or between a register and an immediate are executed. The

ALU operations are divided into three main categories – arithmetic, logical, and bit-functions.

Some implementations of the architecture also provide a powerful multiplier

supporting both signed/unsigned multiplication and fractional format. See the “Instruction

Set” section for a detailed description.

Status Register The Status Register contains information about the result of the most recently executed

arithmetic instruction. This information can be used for altering program flow in order to

perform conditional operations. Note that the Status Register is updated after all ALU

operations, as specified in the Instruction Set Reference. This will in many cases

remove the need for using the dedicated compare instructions, resulting in faster and

more compact code.

The Status Register is not automatically stored when entering an interrupt routine and

restored when returning from an interrupt. This must be handled by software.

The AVR Status Register – SREG – is defined as:

Bit 7 6 5 4 3 2 1 0

I T H S V N Z C SREG

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

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• Bit 7 – I: Global Interrupt Enable

The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual

interrupt enable control is then performed in separate control registers. If the Global

Interrupt Enable Register is cleared, none of the interrupts are enabled independent of

the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt

has occurred, and is set by the RETI instruction to enable subsequent interrupts. The Ibit

can also be set and cleared by the application with the SEI and CLI instructions, as

described in the instruction set reference.

• Bit 6 – T: Bit Copy Storage

The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or

destination for the operated bit. A bit from a register in the Register File can be copied

into T by the BST instruction, and a bit in T can be copied into a bit in a register in the

Register File by the BLD instruction.

• Bit 5 – H: Half Carry Flag

The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry is

useful in BCD arithmetic. See the “Instruction Set Description” for detailed information.

• Bit 4 – S: Sign Bit, S = N ⊕ V

The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement

Overflow Flag V. See the “Instruction Set Description” for detailed information.

• Bit 3 – V: Two’s Complement Overflow Flag

The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See

the “Instruction Set Description” for detailed information.

• Bit 2 – N: Negative Flag

The Negative Flag N indicates a negative result in an arithmetic or logic operation. See

the “Instruction Set Description” for detailed information.

• Bit 1 – Z: Zero Flag

The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the

“Instruction Set Description” for detailed information.

• Bit 0 – C: Carry Flag

The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction

Set Description” for detailed information.

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General Purpose

Register File

The Register File is optimized for the AVR Enhanced RISC instruction set. In order to

achieve the required performance and flexibility, the following input/output schemes are

supported by the Register File:

• One 8-bit output operand and one 8-bit result input

• Two 8-bit output operands and one 8-bit result input

• Two 8-bit output operands and one 16-bit result input

• One 16-bit output operand and one 16-bit result input

Figure 4 shows the structure of the 32 general purpose working registers in the CPU.

Figure 4. AVR CPU General Purpose Working Registers

Most of the instructions operating on the Register File have direct access to all registers,

and most of them are single cycle instructions.

As shown in Figure 4, each register is also assigned a data memory address, mapping

them directly into the first 32 locations of the user Data Space. Although not being physically

implemented as SRAM locations, this memory organization provides great

flexibility in access of the registers, as the X-, Y-, and Z-pointer Registers can be set to

index any register in the file.

7 0 Addr.

R0 $00

R1 $01

R2 $02

…

R13 $0D

General R14 $0E

Purpose R15 $0F

Working R16 $10

Registers R17 $11

…

R26 $1A X-register Low Byte

R27 $1B X-register High Byte

R28 $1C Y-register Low Byte

R29 $1D Y-register High Byte

R30 $1E Z-register Low Byte

R31 $1F Z-register High Byte

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The X-register, Y-register and

Z-register

The registers R26..R31 have some added functions to their general purpose usage.

These registers are 16-bit address pointers for indirect addressing of the Data Space.

The three indirect address registers X, Y, and Z are defined as described in Figure 5.

Figure 5. The X-, Y-, and Z-registers

In the different addressing modes these address registers have functions as fixed displacement,

automatic increment, and automatic decrement (see the Instruction Set

Reference for details).

Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and for

storing return addresses after interrupts and subroutine calls. The Stack Pointer Register

always points to the top of the Stack. Note that the Stack is implemented as growing

from higher memory locations to lower memory locations. This implies that a Stack

PUSH command decreases the Stack Pointer. If software reads the Program Counter

from the Stack after a call or an interrupt, unused bits (15:13) should be masked out.

The Stack Pointer points to the data SRAM Stack area where the Subroutine

and Interrupt

Stacks are located. This Stack space in the data SRAM must be defined by the

program before any subroutine calls are executed or interrupts are enabled. The Stack

Pointer must be set to point above $60. The Stack Pointer is decremented by one when

data is pushed onto the Stack with the PUSH instruction, and it is decremented by two

when the return address is pushed onto the Stack with subroutine call or interrupt. The

Stack Pointer is incremented by one when data is popped from the Stack with the POP

instruction, and it is incremented by two when data is popped from the Stack with return

from subroutine RET or return from interrupt RETI.

The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number

of bits actually used is implementation dependent. Note that the data space in some

implementations of the AVR architecture is so small that only SPL is needed. In this

case, the SPH Register will not be present.

15 XH XL 0

X - register 7 07 0

R27 ($1B) R26 ($1A)

15 YH YL 0

Y - register 7 07 0

R29 ($1D) R28 ($1C)

15 ZH ZL 0

Z - register 7 0 7 0

R31 ($1F) R30 ($1E)

Bit 15 14 13 12 11 10 9 8

SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH

SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL

7 6 5 4 3 2 1 0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

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Instruction Execution

Timing

This section describes the general access timing concepts for instruction execution. The

AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock

source for the chip. No internal clock division is used.

Figure 6 shows the parallel instruction fetches and instruction executions enabled by the

Harvard architecture and the fast-access Register File concept. This is the basic pipelining

concept to obtain up to 1 MIPS per MHz with the corresponding unique results for

functions per cost, functions per clocks, and functions per power-unit.

Figure 6. The Parallel Instruction Fetches and Instruction Executions

Figure 7 shows the internal timing concept for the Register File. In a single clock cycle

an ALU operation using two register operands is executed, and the result is stored back

to the destination register.

Figure 7. Single Cycle ALU Operation

Reset and Interrupt

Handling

The AVR provides several different interrupt sources. These interrupts and the separate

reset vector each have a separate program vector in the program memory space. All

interrupts are assigned individual enable bits which must be written logic one together

with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt.

Depending on the Program Counter value, interrupts may be automatically disabled

when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves software

security. See the section “Memory Programming” on page 262 for details.

The lowest addresses in the program memory space are by default defined as the Reset

and Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 45.

The list also determines the priority levels of the different interrupts. The lower the

address the higher is the priority level. RESET has the highest priority, and next is INT0

clk

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch

2nd Instruction Execute

3rd Instruction Fetch

3rd Instruction Execute

4th Instruction Fetch

T1 T2 T3 T4

CPU

Total Execution Time

Register Operands Fetch

ALU Operation Execute

Result Write Back

T1 T2 T3 T4

clkCPU

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– the External Interrupt Request 0. The Interrupt Vectors can be moved to the start of

the Boot Flash section by setting the IVSEL bit in the General Interrupt Control Register

(GICR). Refer to “Interrupts” on page 45 for more information. The Reset Vector can

also be moved to the start of the boot Flash section by programming the BOOTRST

Fuse, see “Boot Loader Support – Read-While-Write Self-Programming” on page 249.

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts

are disabled. The user software can write logic one to the I-bit to enable nested interrupts.

All enabled interrupts can then interrupt the current interrupt routine. The I-bit is

automatically set when a Return from Interrupt instruction – RETI – is executed.

There are basically two types of interrupts. The first type is triggered by an event that

sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the

actual Interrupt Vector in order to execute the interrupt handling routine, and hardware

clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a

logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the

corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered

until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or

more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding

Interrupt Flag(s) will be set and remembered until the global interrupt enable

bit is set, and will then be executed by order of priority.

The second type of interrupts will trigger as long as the interrupt condition is

present.

These interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears

before the interrupt is enabled, the interrupt will not be triggered.

When the AVR exits from an interrupt, it will always return to the main program and execute

one more instruction before any pending interrupt is served.

Note that the Status Register is not automatically stored when entering an interrupt routine,

nor restored when returning from an interrupt routine. This must be handled by

software.

When using the CLI instruction to disable interrupts, the interrupts will be immediately

disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously

with the CLI instruction. The following example shows how this can be used to

avoid interrupts during the timed EEPROM write sequence.

Assembly Code Example

in r16, SREG ; store SREG value cli ; disable interrupts during timed sequence

sbi EECR, EEMWE ; start EEPROM write sbi EECR, EEWE

out SREG, r16 ; restore SREG value (I-bit) C Code Example

char cSREG;

cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ _CLI();

EECR |= (1<SREG = cSREG; /* restore SREG value (I-bit) */ 15

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When using the SEI instruction to enable interrupts, the instruction following SEI will be

executed before any pending interrupts, as shown in this example.

Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is four clock cycles

minimum. After four clock cycles the program vector address for the actual interrupt

handling routine is executed. During this four clock cycle period, the Program Counter is

pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this

jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle

instruction, this instruction is completed before the interrupt is served. If an interrupt

occurs when the MCU is in sleep mode, the interrupt execution response time is

increased by four clock cycles. This increase comes in addition to the start-up time from

the selected sleep mode.

A return from an interrupt handling routine takes four clock cycles. During these four

clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack

Pointer is incremented by two, and the I-bit in SREG is set.

AVR ATmega16

Memories

This section describes the different memories in the ATmega16. The AVR architecture

has two main memory spaces, the Data Memory and the Program Memory space. In

addition, the ATmega16 features an EEPROM Memory for data storage. All three memory

spaces are linear and regular.

In-System

Reprogrammable Flash

Program Memory

The ATmega16 contains 16K bytes On-chip In-System Reprogrammable Flash memory

for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized

as 8K x 16. For software security, the Flash Program memory space is divided

into two sections, Boot Program section and Application Program section.

The Flash memory has an endurance of at least 10,000 write/erase cycles. The

ATmega16 Program Counter (PC) is 13 bits wide, thus addressing the 8K program

memory locations. The operation of Boot Program section and associated Boot Lock

bits for software protection are described in detail in “Boot Loader Support – Read-

While-Write Self-Programming” on page 249. “Memory Programming” on page 262 contains

a detailed description on Flash data serial downloading using the SPI pins or the

JTAG interface.

Constant tables can be allocated within the entire program memory address space (see

the LPM – Load Program Memory Instruction Description).

Timing diagrams for instruction fetch and execution are presented in “Instruction Execution

Timing” on page 13.

Figure 8. Program Memory Map

$0000

$1FFF

Application Flash Section

Boot Flash Section

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SRAM Data Memory Figure 9 shows how the ATmega16 SRAM Memory is organized.

The lower 1120 Data Memory locations address the Register File, the I/O Memory, and

the internal data SRAM. The first 96 locations address the Register File and I/O Memory,

and the next 1024 locations address the internal data SRAM.

The five different addressing modes for the data memory cover: Direct, Indirect with Displacement,

Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In

the Register File, registers R26 to R31 feature the indirect addressing pointer registers.

The direct addressing reaches the entire data space.

The Indirect with Displacement mode reaches 63 address locations from the base

address given by the Y- or Z-register.

When using register indirect addressing modes with automatic pre-decrement and postincrement,

the address registers X, Y, and Z are decremented or incremented.

The 32 general purpose working registers, 64 I/O Registers, and the 1024 bytes of internal

data SRAM in the ATmega16 are all accessible through all these addressing modes.

The Register File is described in “General Purpose Register File” on page 11.

Figure 9. Data Memory Map

Register File

R0

R1

R2

R29

R30

R31

I/O Registers

$00

$01

$02

...

$3D

$3E

$3F

...

$0000

$0001

$0002

$001D

$001E

$001F

$0020

$0021

$0022

...

$005D

$005E

$005F

...

Data Address Space

$0060

$0061

$045E

$045F

...

Internal SRAM

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Data Memory Access Times This section describes the general access timing concepts for internal memory access.

The internal data SRAM access is performed in two clkCPU cycles as described in Figure

10.

Figure 10. On-chip Data SRAM Access Cycles

EEPROM Data Memory The ATmega16 contains 512 bytes of data EEPROM memory. It is organized as a separate

data space, in which single bytes can be read and written. The EEPROM has an

endurance of at least 100,000 write/erase cycles. The access between the EEPROM

and the CPU is described in the following, specifying the EEPROM Address Registers,

the EEPROM Data Register, and the EEPROM Control Register.

For a detailed description of SPI, JTAG, and Parallel data downloading to the EEPROM,

see page 276, page 281, and page 265, respectively.

EEPROM Read/Write Access The EEPROM Access Registers are accessible in the I/O space.

The write access time for the EEPROM is given in Table 1. A self-timing function, however,

lets the user software detect when the next byte can be written. If the user code

contains instructions that write the EEPROM, some precautions must be taken. In

heavily filtered power supplies, VCC is likely to rise or fall slowly on

Power-up/down. This

causes the device for some period of time to run at a voltage lower than specified as

minimum for the clock frequency used. See “Preventing EEPROM Corruption” on page

22 for details on how to avoid problems in these situations.

In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.

Refer to the description of the EEPROM Control Register for details on this.

When the EEPROM is read, the CPU is halted for four clock cycles before the next

instruction is executed. When the EEPROM is written, the CPU is halted for two clock

cycles before the next instruction is executed.

clk

WR

RD

Data

Data

Address Address Valid

T1 T2 T3

Compute Address

Read Write

CPU

Memory Access Instruction Next Instruction

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The EEPROM Address

Register – EEARH and EEARL

• Bits 15..9 – Res: Reserved Bits

These bits are reserved bits in the ATmega16 and will always read as zero.

• Bits 8..0 – EEAR8..0: EEPROM Address

The EEPROM Address Registers – EEARH and EEARL – specify the EEPROM address

in the 512 bytes EEPROM space. The EEPROM data bytes are addressed linearly

between 0 and 511. The initial value of EEAR is undefined. A proper value must be written

before the EEPROM may be accessed.

The EEPROM Data Register –

EEDR

• Bits 7..0 – EEDR7.0: EEPROM Data

For the EEPROM write operation, the EEDR Register contains the data to be

written to

the EEPROM in the address given by the EEAR Register. For the EEPROM read operation,

the EEDR contains the data read out from the EEPROM at the address given by

EEAR.

The EEPROM Control Register

– EECR

• Bits 7..4 – Res: Reserved Bits

These bits are reserved bits in the ATmega16 and will always read as zero.

• Bit 3 – EERIE: EEPROM Ready Interrupt Enable

Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set.

Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a

constant interrupt when EEWE is cleared.

• Bit 2 – EEMWE: EEPROM Master Write Enable

The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be

written. When EEMWE is set, setting EEWE within four clock cycles will write data to the

EEPROM at the selected address If EEMWE is zero, setting EEWE will have no effect.

Bit 15 14 13 12 11 10 9 8

– – – – – – – EEAR8 EEARH

EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL

7 6 5 4 3 2 1 0

Read/Write R R R R R R R R/W

R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 X

X X X X X X X X

Bit 7 6 5 4 3 2 1 0

MSB LSB EEDR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0

– – – – EERIE EEMWE EEWE EERE EECR

Read/Write R R R R R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 X 0

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When EEMWE has been written to one by software, hardware clears the bit to zero after

four clock cycles. See the description of the EEWE bit for an EEPROM write procedure.

• Bit 1 – EEWE: EEPROM Write Enable

The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When

address and data are correctly set up, the EEWE bit must be written to one to write the

value into the EEPROM. The EEMWE bit must be written to one before a logical one is

written to EEWE, otherwise no EEPROM write takes place. The following procedure

should be followed when writing the EEPROM (the order of steps 3 and 4 is not

essential):

1. Wait until EEWE becomes zero.

2. Wait until SPMEN in SPMCR becomes zero.

3. Write new EEPROM address to EEAR (optional).

4. Write new EEPROM data to EEDR (optional).

5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR.

6. Within four clock cycles after setting EEMWE, write a logical one to EEWE.

The EEPROM can not be programmed during a CPU write to the Flash memory. The

software must check that the Flash programming is completed before initiating a new

EEPROM write. Step 2 is only relevant if the software contains a Boot Loader allowing

the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2

can be omitted. See “Boot Loader Support – Read-While-Write Self-Programming” on

page 249 for details about boot programming.

Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the

EEPROM Master Write Enable will time-out. If an interrupt routine accessing the

EEPROM is interrupting another EEPROM Access, the EEAR or EEDR reGister will be

modified, causing the interrupted EEPROM Access to fail. It is recommended to have

the Global Interrupt Flag cleared during all the steps to avoid these problems.

When the write access time has elapsed, the EEWE bit is cleared by hardware. The

user software can poll this bit and wait for a zero before writing the next byte. When

EEWE has been set, the CPU is halted for two cycles before the next instruction is

executed.

• Bit 0 – EERE: EEPROM Read Enable

The EEPROM Read Enable Signal – EERE – is the read strobe to the EEPROM. When

the correct address is set up in the EEAR Register, the EERE bit must be written to a

logic one to trigger the EEPROM read. The EEPROM read access takes one instruction,

and the requested data is available immediately. When the EEPROM is read, the CPU

is halted for four cycles before the next instruction is executed.

The user should poll the EEWE bit before starting the read operation. If a write operation

is in progress, it is neither possible to read the EEPROM, nor to change the EEAR

Register.

The calibrated Oscillator is used to time the EEPROM accesses. Table 1 lists the typical

programming time for EEPROM access from the CPU.

Table 1. EEPROM Programming Time

Symbol

Number of Calibrated RC

Oscillator Cycles(1) Typ Programming Time

EEPROM write (from CPU) 8448 8.5 ms

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Note: 1. Uses 1 MHz clock, independent of CKSEL Fuse setting.

The following code examples show one assembly and one C function for writing to the

EEPROM. The examples assume that interrupts are controlled (for example by disabling

interrupts globally) so that no interrupts will occur during execution of these

functions. The examples also assume that no Flash Boot Loader is present in the software.

If such code is present, the EEPROM write function must also wait for any

ongoing SPM command to finish.

Assembly Code Example

EEPROM_write:

; Wait for completion of previous write sbic EECR,EEWE

rjmp EEPROM_write

; Set up address (r18:r17) in address register out EEARH, r18

out EEARL, r17

; Write data (r16) to data register out EEDR,r16

; Write logical one to EEMWE sbi EECR,EEMWE

; Start eeprom write by setting EEWE

sbi EECR,EEWE

ret

C Code Example

void EEPROM_write(unsigned int uiAddress, unsigned char ucData)

{

/* Wait for completion of previous write */

while(EECR & (1<;

/* Set up address and data registers */

EEAR = uiAddress;

EEDR = ucData;

/* Write logical one to EEMWE */ EECR |= (1</* Start eeprom write by setting EEWE */ EECR |= (1<}

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The next code examples show assembly and C functions for reading the EEPROM. The

examples assume that interrupts are controlled so that no interrupts will occur during

execution of these functions.

EEPROM Write During Powerdown

Sleep Mode

When entering Power-down Sleep mode while an EEPROM write operation is active,

the EEPROM write operation will continue, and will complete before the Write

Access

time has passed. However, when the write operation is completed, the Oscillator continues

running, and as a consequence, the device does not enter Power-down entirely. It is

therefore recommended to verify that the EEPROM write operation is completed before

entering Power-down.

Preventing EEPROM

Corruption

During periods of low VCC, the EEPROM data can be corrupted because the supply voltage

is too low for the CPU and the EEPROM to operate properly. These issues are the

same as for board level systems using EEPROM, and the same design solutions should

be applied.

An EEPROM data corruption can be caused by two situations when the voltage is too

low. First, a regular write sequence to the EEPROM requires a minimum voltage to

operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the

supply voltage is too low.

Assembly Code Example

EEPROM_read:

; Wait for completion of previous write sbic EECR,EEWE

rjmp EEPROM_read

; Set up address (r18:r17) in address register out EEARH, r18

out EEARL, r17

; Start eeprom read by writing EERE sbi EECR,EERE

; Read data from data register in r16,EEDR

ret

C Code Example

unsigned char EEPROM_read(unsigned int uiAddress)

{

/* Wait for completion of previous write */ while(EECR & (1<;

/* Set up address register */

EEAR = uiAddress;

/* Start eeprom read by writing EERE */ EECR |= (1</* Return data from data register */ return EEDR;

}

23

ATmega16(L)

2466N–AVR–10/06

EEPROM data corruption can easily be avoided by following this design

recommendation:

Keep the AVR RESET active (low) during periods of insufficient power supply voltage.

This can be done by enabling the internal Brown-out Detector (BOD). If the

detection level of the internal BOD does not match the needed detection level, an

external low VCC Reset Protection circuit can be used. If a reset occurs while a write

operation is in progress, the write operation will be completed provided that the

power supply voltage is sufficient.

I/O Memory The I/O space definition of the ATmega16 is shown in “Register Summary” on page 334.

All ATmega16 I/Os and peripherals are placed in the I/O space. The I/O locations are

accessed by the IN and OUT instructions, transferring data between the 32 general purpose

working registers and the I/O space. I/O Registers within the address range $00 -

$1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the

value of single bits can be checked by using the SBIS and SBIC instructions. Refer to

the Instruction Set section for more details. When using the I/O specific commands IN

and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O Registers as

data space using LD and ST instructions, $20 must be added to these addresses.

For compatibility with future devices, reserved bits should be written to zero if accessed.

Reserved I/O memory addresses should never be written.

Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI

and SBI instructions will operate on all bits in the I/O Register, writing a one back into

any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers

$00 to $1F only.

The I/O and Peripherals Control Registers are explained in later sections.