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This Manual: http://www.manuallib.com/file/2586955LTC4218Hot Swap ControllerFEATURES
■ ■ ■ ■ ■ ■ ■DESCRIPTION
The LTC®4218 is a Hot Swap™ controller that allows a board to be safely inserted and removed from a live backplane. An internal high side switch driver controls the gate of an external N-channel MOSFET for supply voltages from 2.9V to 26.5V. A dedicated 12V version (LTC4218-12) contains preset 12V specifi c thresholds, while the standard LTC4218 allows adjustable thresholds.The LTC4218 provides an accurate (5%) current limit with current foldback limiting. The current limit threshold can be adjusted dynamically using an external pin. Additional features include a current monitor output that amplifi es the sense voltage for ground referenced current sensing. Overvoltage, undervoltage and powergood monitoring are also provided., LT, LTC and LTM are registered trademarks of Linear Technology Corporation. Hot Swap is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners.
Wide Operating Voltage Range: 2.9V to 26.5VAdjustable, 5% Accurate (15mV) Current LimitCurrent Monitor OutputAdjustable Current Limit Timer Before FaultPowergood and Fault OutputsAdjustable Inrush Current Control2% Accurate Undervoltage and Overvoltage Protection■ Available in 16-Lead SSOP and 16-Pin 5mm × 3mm DFN PackagesAPPLICATIONS
RAID Systems■ ATCA, AMC, μTCA Systems■ Server I/O Cards■ Industrial■TYPICAL APPLICATION
12V, 6A Card Resident Application12V2mΩSi7108DNVOUT12V6A330μFVIN10V/DIVIIN1A/DIVVOUT10V/DIVPG10V/DIV
4218 TA01b
Power-Up Waveform+10ΩSENSE–SENSEVDDAUTORETRYUVLTC4218DHC-12FLTTIMER0.1μF0.1μFINTVCCGNDIMON20kPG10k+GATESOURCE12V1k0.01μF25ms/DIV
ADC4218 TA01a4218f1This Manual: http://www.manuallib.com/file/2586955LTC4218ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)Supply Voltage (VDD) .................................–0.3V to 35VInput VoltagesFB, OV, UV .............................................–0.3V to 12VTIMER ...................................................–0.3V to 3.5VSENSE– .............................VDD – 10V or –0.3V to VDDSENSE+ .............................VDD – 10V or –0.3V to VDDSOURCE ........................................– 5V to VDD + 0.3VOutput VoltagesISET, IMON .................................................–0.3V to 3VPG, FLT ..................................................–0.3V to 35VINTVCC ..................................................–0.3V to 3.5VGATE (Note 3) ........................................–0.3V to 35V Operating Temperature RangeLTC4218C ................................................0°C to 70°CLTC4218I .............................................–40°C to 85°CStorage Temperature RangeDHC Package .....................................–65°C to 125°CGN Package .......................................–65°C to 150°CLead Temperature (Soldering, 10 sec)GN Package Only ..............................................300°CPIN CONFIGURATION
TOP VIEWNCVDDUVOVTIMERINTVCCGNDSOURCE123456781716SENSE+15SENSE–14ISET13IMON12FB11FLT10PG9GATENCVDDUVOVTIMERINTVCCGNDSOURCE12345678TOP VIEW16SENSE+15SENSE–14ISET13IMON12FB11FLT10PG9GATEDHC PACKAGE16-LEAD (5mm × 3mm) PLASTIC DFNTJMAX = 125°C, θJA = 43°C/WEXPOSED PAD (PIN 17) IS SUBSTRATE GNDGN PACKAGE16-LEAD PLASTIC SSOPTJMAX = 150°C, θJA = 135°C/WORDER INFORMATION
LEAD FREE FINISHLTC4218CDHC-12#PBFLTC4218IDHC-12#PBFLTC4218CGN#PBFLTC4218IGN#PBFTAPE AND REELLTC4218CDHC-12#TRPBFLTC4218IDHC-12#TRPBFLTC4218CGN#TRPBFLTC4218IGN#TRPBFPART MARKING*42181242181242184218PACKAGE DESCRIPTION16-Lead (5mm × 3mm) Plastic DFN16-Lead (5mm × 3mm) Plastic DFN16-Lead Plastic SSOP16-Lead Plastic SSOPTEMPERATURE RANGE0°C to 70°C–40°C to 85°C0°C to 70°C–40°C to 85°CConsult LTC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container.Consult LTC Marketing for information on non-standard lead based fi nish parts.For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/4218f2This Manual: http://www.manuallib.com/file/2586955LTC4218ELECTRICAL CHARACTERISTICS The ● denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VDD = 12V unless otherwise noted.PARAMETERInput Supply RangeInput Supply CurrentInput Supply Undervoltage LockoutInput Supply Undervoltage ThresholdInput Supply Undervoltage HysteresisInput Supply Overvoltage ThresholdInput Supply Overvoltage HysteresisSOURCE Powergood ThresholdCurrent Limit Sense Voltage Threshold (VSENSE+ – VSENSE–)SENSE– Pin Input CurrentSENSE+ Pin Input CurrentExternal N-Channel Gate Drive (VGATE – VSOURCE)Gate High Threshold (VGATE – VSOURCE) External N-Channel Gate Pull-Up CurrentExternal N-Channel Gate Fast Pulldown CurrentExternal N-Channel Gate Pulldown CurrentGate Drive On, VGATE = VSOURCE = 12VFast Turn Off, VGATE = 18V, VSOURCE =12VGate Drive Off, VGATE = 18V, VSOURCE =12VVIN = 1.2V, LTC4218 OnlyLTC4218-12 OnlyVIN RisingFET OnVDD RisingLTC4218-12 Only VDD RisingLTC4218-12 OnlyLTC4218-12 Only VDD RisingLTC4218-12 OnlyLTC4218-12 Only VSOURCE RisingLTC4218-12 OnlyVFB = 1.23VVFB = 0VVFB = 1.23V, RSET = 20kΩVSENSE– = 12V VSENSE+ = 12V VDD = 2.9V to 26.5V (Note 3)IGATE = 0, –1μACONDITIONS●●●●●●●●●●●●●●●●●●●SYMBOLDC CharacteristicsVDDIDDVDD(UVL)VDD(UVTH)ΔVDD(UVHYST)VDD(OVTH)ΔVDD(OVHYST)VSOURCE(PGTH)ΔVSNS(TH)MIN2.9TYPMAX26.5UNITSVmAVVmVVmVVmVmVmVmVμAμAVVμAmAμA1.62.659.658014.723010.215014.252.86.72.739.8865015.0527010.5175153.757.545.553.5–191202006.154.2–2417025052.8510.270015.430010.820015.754.78.325±10±206.54.8–29220340ΔVSOURCE(PGHYST)SOURCE Powergood HysteresisISENSE–(IN)ISENSE+(IN)ΔVGATEΔVGATE-HIGH(TH)IGATE(UP)IGATE(FST)IGATE(DN)InputsI(IN)R(IN)V(TH)ΔVOV(HYST)ΔVUV(HYST)VUV(RTH)ΔVFB(HYST)RISETISOURCEOV, UV, FB Pin Input CurrentOV, UV, FB Pin Input ResistanceOV, UV, FB Pin Threshold VoltageOV Pin HysteresisUV Pin HysteresisUV Pin Reset Threshold VoltageFB Pin Power Good HysteresisISET Pin Output ResistorSOURCE Pin Input Current●●●●●0131.2110500.551019.5501181.23520800.62202070200.401.20.1–801.41.2350.21–1002±1231.26301100.73020.5904±10.8±101.280.3–1202.6μAkΩVmVmVVmVkΩμAμAμAVμAVVμAμA4218fVUV Falling●●●VSOURCE = VGATE = 12V, LTC4218-12 Only●●VSOURCE = VGATE = 12V, LTC4218 Only●VSOURCE = VGATE = 0VIOUT = 2mAVOUT = 30VVTIMER RisingVTIMER FallingVTIMER = 0VVTIMER = 1.2V●●●●●●OutputsV(OL)I(OH)VTIMER(H)VTIMER(L)ITIMER(UP)ITIMER(DN)PG, FLT Pin Output Low VoltagePG, FLT Pin Input Leakage CurrentTIMER Pin High ThresholdTIMER Pin Low ThresholdTIMER Pin Pull Up CurrentTIMER Pin Pulldown Current3This Manual: http://www.manuallib.com/file/2586955LTC4218ELECTRICAL CHARACTERISTICS The ● denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VDD = 12V unless otherwise noted.SYMBOLITIMER(RATIO)IMON(FS)IMON(OFF)GIMONAC CharacteristicstPHL(GATE)tPHL(SENSE)Input High (OV), Input Low (UV) to GATE Low Propagation DelayVSENSE+ – VSENSE– High to GATE Low Propagation DelayTurn-On DelayVGATE < 16.5V FallingVFB = 0, Step (VSENSE+ – VSENSE–) to 60mV, CGATE = 1.5nF, VGATE < 16.5V FallingStep VUV to 2V, VGATE > 13V●●PARAMETERTIMER Pin Current Ratio ITIMER(DN)/ITIMER(UP)IMON Fullscale Output CurrentIMON Pin Offset CurrentIMON Pin GainCONDITIONS●MIN1.6946.47TYP2100±06.6730.2MAX2.7106±66.8751UNITS%μAμAμA/mVμsμsVSENSE+ – VSENSE– = 15mVVSENSE+ – VSENSE– = 1mVVSENSE+ – VSENSE– = 15mV and 1mV●●●tD(ON)●50100150msNote 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.Note 2: All currents into pins are positive, all voltages are referenced to GND unless otherwise specifi ed.Note 3: An internal clamp limits the GATE pin to a maximum of 6.5V above the SOURCE pin. Driving either GATE or SOURCE pin to voltages beyond the clamp may damage the device.4218f4This Manual: http://www.manuallib.com/file/2586955LTC4218TYPICAL PERFORMANCE CHARACTERISTICS
IDD vs VDD2.0
3.53.0
1.8
85°CIDD (mA)1.6
25°C1.4
–40°C1.21.0
INTVCC (V)2.52.01.51.00.50
1.226
–50
VDD = 3.3VVDD = 5VUV LOW-HIGH HRESHOLD (V)1.232
TA = 25°C, VDD = 12V unless otherwise noted.UV Low-High Threshold vs Temperature1.234
INTVCC Load Regulation1.230
1.228
0510
15VDD (V)
202530
4218 G01
0–2–4
–8
ILOAD (mA)
–6–10–12–14–25
50025
TEMPERATURE (°C)
75100
4218 G03
4218 G02
UV Hysteresis vs Temperature0.10
TIMER PULL-UP CURRENT (μA)–110
Timer Pull-Up Current vs TemperatureCURRENT LIMIT PROPAGATION DELAY (μs)1000
Current Limit DelayCGATE = 10nF–105100
UV HYSTERESIS (V)0.08
–10010
0.06
–951
0.04
–50
–25
50025
TEMPERATURE (°C)
75100
4218 G04
–90–50
0.1
0
15304560CURRENT LIMIT SENSE VOLTAGE
(VSENSE+ – VSENSE–) (mV)
75
–25
02550TEMPERATURE (°C)
75100
4218 G05
4218 G06
Current Limit Threshold Foldback16CURRENT LIMIT SENSE VOLTAGE (VSENSE+ – VSENSE–) (mV)CURRENT LIMIT SENSE VOLTAGE (VDD – VSENSE) (mV)141210864200
0.2
0.40.60.8FB VOLTAGE (V)
1.0
1.2
4218 G07
Current Limit Adjustment161412
RISET (kΩ)1k
10k
100kRSET (Ω)
1M
10M
4218 G08
ISET Resistor vs Temperature22
21
1086420
20
19
18–50
–25
50025
TEMPERATURE (°C)
75100
4218 G09
4218f5This Manual: http://www.manuallib.com/file/2586955LTC4218TYPICAL PERFORMANCE CHARACTERISTICS
GATE Pull-Up Current vs Temperature–26.0
GATE DRIVE (VGATE – VSOURCE) (V)7
VDD = 12VGATE DRIVE (VGATE – VSOURCE) (V)–25
–30
4218 G11
TA = 25°C, VDD = 12V unless otherwise noted.Gate Pull-Up Current vs Gate Drive6.2
6543
VDD = 3.3V210
Gate Drive vs VDD–25.5IGATE PULL-UP (μA)6.0
5.8
–25.0
5.6
–24.5
5.4
–24.0
–50
5.2
0
–5
–10
–15–20IGATE (μA)
0
5
10
15VDD (V)
20
25
30
4218 G12
–25
50025
TEMPERATURE (°C)
75100
4218 G10
Gate Drive vs Temperature6.15GATE DRIVE (VGATE – VSOURCE) (V)1412
6.14
PG, FLT VOUT LOW (V)10864
PG, FLT VOUT Low vs ILOAD105
IMON vs Temperature and VDDVDD = 3.3V, 12V, 24VVSENSE+ – VSENSE– = 15mVPGFLT100
6.12
IMON (μA)0
2
4
68ILOAD (mA)
10
12
4218 G14
6.1395
90
6.11
2
6.10
–50
0
–25
02550TEMPERATURE (°C)
75
100
4218 G13
85
80–50
–25
02550TEMPERATURE (°C)
75100
4218 G15
IMON vs Sense100
4
VIMON vs Sense75IMON (μA)VIMON (V)3
RIMON = 100kRIMON = 40k502RIMON = 20k251
RIMON = 10k0
0
510SENSE VOLTAGE (mV)
15
4218 G16
0
0
510SENSE VOLTAGE (mV)
15
4218 G17
4218f6This Manual: http://www.manuallib.com/file/2586955LTC4218PIN FUNCTIONS
Exposed Pad: Exposed pad may be left open or connected to device ground.FB: Foldback and Power Good Comparator Input. Connect this pin to an external resistive divider from SOURCE for the LTC4218 (adjustable version). The LTC4218-12 ver-sion uses a fi xed internal divider with optional external adjustment. Open the pin if the LTC4218-12 thresholds for 12V operation are desired. If the voltage falls below 0.6V, the output power is considered bad and the current limit is reduced. If the voltage falls below 1.21V the PG pin will pull low to indicate the power is bad.FLT: Overcurrent Fault Indicator. Open drain output pulls low when an overcurrent fault has occurred and the circuit breaker trips. For overcurrent auto-retry tie to UV pin (see Applications Information for details).GATE: Gate Drive for External N-Channel FET. An internal 24μA current source charges the gate of the external N-channel MOSFET. A resistor and capacitor network from this pin to ground sets the turn-on rate. During an undervoltage or overvoltage generated turn-off a 250μA pulldown current turns the MOSFET off. During a short circuit or undervoltage lockout, a 170mA pulldown current source between GATE and SOURCE is activated.GND: Device Ground.IMON: Current Monitor Output. The current sourced from this pin is defi ned as the current sense voltage (between the SENSE+ and SENSE– pins) multiplied by 6.67μA/mV. Placing a 20k resistor from this pin to GND creates a 0V to 2V voltage swing when the current sense voltage ranges from 0mV to 15mV.INTVCC: Internal 3V Supply Decoupling Output. This pin must have a 0.1μF or larger capacitor.ISET: Current Limit Adjustment Pin. For 15mV current limit threshold, open this pin. This pin is driven by a 20k resis-tor in series with a voltage source. The pin voltage is used to generate the current limit threshold. The internal 20k resistor and an external resistor between ISET and ground create an attenuator that lowers the current limit value.NC: No ConnectionOV: Overvoltage Comparator Input. Connect this pin to an external resistive divider from VDD for the LTC4218 (adjustable version). The LTC4218-12 version uses a fi xed internal divider with optional external adjustment for 12V operation. Open the pin if the LTC4218-12 thresholds are desired. If the voltage at this pin rises above 1.235V, an overvoltage is detected and the switch turns off. Tie to GND if unused.PG: Power Good Indicator. Open drain output pulls low when the FB pin drops below 1.21V indicating the power is bad.SENSE–: Current Sense Minus Input. Connect this pin to the opposite of VDD current sense resistor side. The cur-rent limit circuit controls the GATE pin to limit the sense voltage between the SENSE+ and SENSE– pins to 15mV or less depending on the voltage at the FB pin.SENSE+: Current Sense Plus Input. Connect this pin to the VDD side of the current sense resistor.SOURCE: N-Channel MOSFET Source Connection. Connect this pin to the source of the external N-channel MOSFET switch. This pin provides a return for the gate pulldown circuit. In the LTC4218-12 version, the powergood com-parator monitors an internal resistive divider between the SOURCE pin and GND.TIMER: Timer Input. Connect a capacitor between this pin and ground to set a 12ms/μF duration for current limit before the switch is turned off. If the UV pin is toggled low while the MOSFET switch is off, the switch will turn on again following a cool down time of 518ms/μF duration.UV: Undervoltage Comparator Input. Tie high if unused. Connect this pin to an external resistive divider from VDD for the LTC4218 (adjustable version). The LTC4218-12 version drives the UV pin with an internal resistive divider from VDD. Open the pin if the preset LTC4218-12 thresh-olds for 12V operation are desired. If the UV pin voltage falls below 1.15V, an undervoltage is detected and the switch turns off. Pulling this pin below 0.62V resets the overcurrent fault and allows the switch to turn back on (see Applications Information for details). If overcurrent auto-retry is desired then tie this pin to the FLT pin.VDD: Supply Voltage. This pin has an undervoltage lockout threshold of 2.73V.4218f7This Manual: http://www.manuallib.com/file/2586955LTC4218FUNCTIONAL DIAGRAM
SENSE+
SENSE–
GATE
SOURCE
VDD
IMON
–CSCLAMPCHARGEPUMPAND GATEDRIVERISET
20k0.6VREFERENCEX1+–+CMFOLDBACK0.6VSOURCE150k1.235V*FB
140kUV
20k*UVPGLOGIC*0.62V+RSTVDD224kOV
20k*1.235V*–+OV0.2V+TM1INTVCC100μA–––UVLO12μA+TM2VDD3.1VGEN1.235VVDD–TIMERUVLO2GND
* DFN ONLY
EXPOSED PAD*
8This Manual: http://www.manuallib.com/file/2586955–2.73V+–+–+20k1.235VPG*FLTINTVCC
2.65V4218 BDVDD+4218fLTC4218OPERATION
The Functional Diagram displays the main circuits of the device. The LTC4218 is designed to turn a board’s sup-ply voltage on and off in a controlled manner, allowing the board to be safely inserted and removed from a live backplane. During normal operation, the charge pump and gate driver turn on the external N-channel pass FET’s gate to provide power to the load.The current sense (CS) amplifi er monitors the load current using the voltage sensed across the current sense resistor. The CS amplifi er limits the current in the load by reducing the GATE-to-SOURCE voltage in an active control loop. It is simple to adjust the current limit threshold using the current setting (ISET) pin. This allows a different threshold during other times such as startup.A short circuit on the output to ground causes signifi cant power dissipation during active current limiting. To limit this power, the foldback amplifi er reduces the current limit value from 15mV to 3.75mV (referred to the SENSE+ minus SENSE– voltage) in a linear manner as the FB pin drops below 0.6V (see Typical Performance Characteristics).If an overcurrent condition persists, the TIMER pin ramps up with a 100μA current source until the pin voltage exceeds 1.2V (comparator TM2). This indicates to the logic that it is time to turn off the MOSFET to prevent overheating. At this point the TIMER pin ramps down using the 2μA current source until the voltage drops below 0.2V (Comparator TM1) which tells the logic to start an internal 100ms timer. At this point, the pass transistor has cooled and it is safe to turn it on again.The fi xed 12V version, LTC4218-12, uses two separate internal dividers from VDD to drive the UV and OV pins. This version also features a divider from the SOURCE pin to drive the FB pin. The LTC4218-12 is available in a DFN package while the LTC4218 (adjustable version) is in a SSOP package.The output voltage is monitored using the FB pin and the PG comparator to determine if the power is available for the load. The power good condition is signaled by the PG pin using an open-drain pulldown transistor.The Functional Diagram shows the monitoring blocks of the LTC4218. The comparators on the left side include the UV and OV comparators. These comparators are used to determine if the external conditions are valid prior to turning on the MOSFET. But fi rst, the undervoltage lockout circuits (UVLO1 and UVLO2) must validate the input supply and internally generated 3.1V supply (INTVCC) and gener-ate the power up initialization to the logic circuits. If the external conditions remain valid for 100ms the MOSFET is allowed to turn on.Other monitoring features include the IMON current monitor. The current monitor (CM) outputs a current proportional to the sense resistor current. This current can drive an external resistor or other circuits for monitoring purposes.4218f9This Manual: http://www.manuallib.com/file/2586955LTC4218APPLICATIONS INFORMATION
The typical LTC4218 application is in a high availability system that uses a positive voltage supply to distribute power to individual cards. The basic application circuit is shown in Figure 1. External component selection is discussed in detail in the following sections.RS2mΩ12VQ1Si7108DNVOUT12V3AThe pass transistor is turned on by charging up the GATE with a 24μA charge pump generated current source (Figure 2).VDD + 6.15
SLOPE = 24μA/CGATE
VDD
SOURCEGATE
R110ΩSENSE–GATESOURCESENSE+VDDR4140kUVR2224kR320kR520kFLTOVLTC4218GNPGISETRSET20kCT0.1μFTIMERC10.1μFINTVCCGNDIMONADCRMON20k4218 F01FBRGATE1kCGATE0.01μFR6150k12VR810kR720k+CL330μFt1t2
4218 F02
Figure 2. Supply Turn-OnThe voltage at the GATE pin rises with a slope equal to 24μA/CGATE and the supply inrush current is set at: IINRUSH=
CLCGATE
•24µA
Figure 1. 3A, 12V Card Resident ApplicationTurn-On SequenceThe power supply on a board is controlled by placing an external N-channel pass transistor (Q1) in the power path. Note the sense resistor (RS) detects current and the capacitor (CGATE) controls gate slew rate. Resistor R1 prevents high frequency oscillations in Q1 and resistor RGATE isolates CGATE during fast turn-off.Several conditions must be present before the external pass transistor can be turned on. First, the supply VDD must exceed its undervoltage lockout level. Next, the internally generated supply INTVCC must cross its 2.65V undervoltage threshold. This generates a 25μs power-on-reset pulse which clears the logic’s fault register and initializes internal latches.After the power-on-reset pulse, the LTC4218 will go through the following sequence. First, the UV and OV pins must indicate that the input power is within the acceptable range. All of these conditions must be satisfi ed for a duration of 100ms to ensure that any contact bounce during the insertion has ended.When the GATE voltage reaches the MOSFET threshold voltage, the switch begins to turn on and the SOURCE voltage follows the GATE voltage as it increases. Once SOURCE reaches VDD, the GATE will ramp up until clamped by the 6.15V zener between GATE and SOURCE.As the SOURCE pin voltage rises, so will the FB pin which is monitoring it. If the voltage across the current sense resistor (RS) gets too high, the inrush current will be limited by the internal current limiting circuitry. Once the FB pin crosses its 1.235V threshold and the GATE to SOURCE voltage exceeds 4.2V, the PG pin will cease to pull low and indicate that the power is good.Turn-Off SequenceThe switch can be turned off by a variety of conditions. A normal turn-off is initiated by the UV pin going below its 1.235V threshold. Additionally, several fault conditions will turn off the switch. These include an input overvoltage (OV pin) and overcurrent circuit breaker (SENSE pin). Normally, the switch is turned off with a 250μA current pulling down the GATE pin to ground. With the switch turned off, the SOURCE pin voltage drops which pulls the FB pin below 4218f10This Manual: http://www.manuallib.com/file/2586955LTC4218APPLICATIONS INFORMATION
its threshold. The PG then pulls low to indicate output power is no longer good.If VDD drops below 2.65V for greater than 5μs or INTVCC drops below 2.5V for greater than 1μs, a fast shutdown of the switch is initiated. The GATE is pulled down with a 170mA current to the SOURCE pin.Overcurrent FaultThe LTC4218 features an adjustable current limit with foldback that protects the MOSFET when excessive load current happens. To protect the switch during active cur-rent limit, the available current is reduced as a function of the output voltage sensed by the FB pin. A graph in the Typical Performance Characteristics shows the current limit versus FB voltage.An overcurrent fault occurs when the current limit circuitry has been engaged for longer than the time-out delay set by the TIMER. Current limiting begins when the current sense voltage between the SENSE+ and SENSE– pins reaches 3.75mV to 15mV (depending on the foldback). The GATE pin is then brought down with a 170mA GATE-to-SOURCE current. The voltage on the GATE is regulated in order to limit the current sense voltage to less than 15mV. At this point, a circuit breaker time delay starts by charging the external timing capacitor from the TIMER pin with a 100μA pull-up current. If the TIMER pin reaches its 1.2V thresh-old, the external switch turns off (with a 250μA current from GATE to ground). Next, the FLT pin is pulled low to indicate an overcurrent fault has turned off the MOSFET. For a given the circuit breaker time delay, the equation for setting the timing capacitor’s value is as follows: CT = TCB • 0.083[μF/ms]After the switch is turned off, the TIMER pin begins dis-charging the timing capacitor with a 2μA pulldown current. When the TIMER pin reaches its 0.2V threshold, the switch is allowed to turn on again if the overcurrent fault has been cleared. Bringing the UV pin below 0.6V and then high will clear the fault. If the TIMER pin is tied to INTVCC, then the switch is allowed to turn on again (after an internal 100ms delay) if the overcurrent fault is cleared.Tying the FLT pin to the UV pin allows the part to self-clear the fault and turn the MOSFET on as soon as TIMER pin has ramped below 0.2V. In this auto retry mode, the LTC4218 repeatedly tries to turn on after an overcurrent at a period determined by the capacitor on the TIMER pin.The waveform in Figure 3 shows how the output latches off following a short circuit. The drop across the sense resistor is 3.75mV as the timer ramps up.VOUT10V/DIVIOUT2A/DIV
ΔVGATE10V/DIVTIMER2V/DIV
1ms/DIV
4218 F03
Figure 3. Short-Circuit WaveformCurrent Limit AdjustmentThe default value of the active current limiting signal threshold is 15mV. The current limit threshold can be adjusted lower by placing a resistor on the ISET pin. As shown in the Functional Diagram the voltage at the ISET pin (via the clamp circuit) sets the CS amplifi er’s built-in offset voltage. This offset voltage directly determines the active current limit value. With the ISET pin open, the volt-age at the ISET pin is determined by the buffered reference voltage. This voltage is set to 0.618V which corresponds to a 15mV current limit threshold.An external resistor placed between the ISET pin and ground forms a resistive divider with the internal 20k sourcing resistor. The divider acts to lower the voltage at the ISET pin and therefore lower the current limit threshold. The overall current limit threshold precision is reduced to ±11% when using a 20k resistor to half the threshold.4218f11This Manual: http://www.manuallib.com/file/2586955LTC4218APPLICATIONS INFORMATION
Using a switch (connected to ground) in series with the external resistor allows the active current limit to change only when the switch is closed. This feature can be used when the startup current exceeds the typical maximum load current.Monitor MOSFET CurrentThe current in the MOSFET passes through the sense resistor. The voltage on the sense resistor is converted to a current that is sourced out of the IMON pin. The gain of er is 100μA from IMON for 15mV on the the ISENSE amplifisense resistor. This output current can be converted to a voltage using an external resistor to drive a comparator or ADC. The voltage compliance for the IMON pin is from 0V to INTVCC – 0.7V.A microcontroller with a built-in comparator can build a simple integrating single-slope ADC by resetting a capaci-tor that is charged with this current. When the capacitor voltage trips the comparator and the capacitor is reset, a timer is started. The time between resets will indicate the MOSFET current.Monitor OV and UV FaultsProtecting the load from an overvoltage condition is the main function of the OV pin. In the LTC4218-12 an internal resistive divider (driving the OV pin) connects to a compara-tor to turn off the MOSFET when the VDD voltage exceeds 15.05V. If the VDD pin subsequently falls back below 14.8V, the switch will be allowed to turn on immediately. In the LTC4218, the OV pin threshold is 1.23V when rising and 1.21V when falling out of overvoltage.The UV pin functions as an undervoltage protection pin or as an “on” pin. In the LTC4218-12 the MOSFET turns off when VDD falls below 9.23V. If the VDD pin subsequently rises above 9.88V for 100ms, the switch will be allowed to turn on again. The LTC4218 UV turn on/off threshold is 1.23V (rising) and 1.15V (falling).In the case of an undervoltage or overvoltage, the MOSFET turns off and there is indication on the PG status pin. When the overvoltage is removed, the MOSFET’s gate ramps up immediately.Powergood IndicationIn addition to setting the foldback current limit threshold, the FB pin is used to determine a powergood condition. The LTC4218-12 uses an internal resistive divider on the SOURCE pin to drive the FB pin. The PG comparator indicates logic high when SOURCE pin rises above 10.5V. If the VDD pin subsequently falls below 10.3V, the com-parator toggles low. On the LTC4218 the PG comparator drives high when the FB pin rises above 1.23V and low when falls below 1.21V.Once the PG comparator is high, the GATE pin voltage is monitored with respect to the SOURCE pin. Once the GATE minus SOURCE voltage exceeds 4.2V, the PG pin goes high. This indicates to the system that it is safe to load the Output while the MOSFET is completely turned “on”. The PG pin goes low when the GATE is commanded off (using the UV, OV or SENSE+/SENSE– pins) or when the PG comparator drives low.12V Fixed VersionIn the LTC4218-12, the UV, OV and FB pins are driven by internal dividers which may need to be fi ltered to prevent false faults. By placing a bypass capacitor on these pins the faults are delayed by the RC time constant. Use the RIN value from the electrical table for this calculation.In cases where the fi xed thresholds need a slight adjust-ment, placing a resistor from the UV or OV pins to VDD or GND will adjust the threshold up or down. Likewise, placing a resistor between FB pin to OUT or GND adjusts the threshold. Again, use the RIN value from the electrical table for this calculation.An example in Figure 4 raises the UV turn-on voltage from 9.88V to 10.5V. Increasing the UV level requires adding a resistor between UV and ground. The resistor, (RSHUNT1), can be calculated using electrical table parameters as follows:RSHUNT1= (VNEW–VOLD)R(IN)•VOLD
=
18k•9.88
=287k
(10.5–9.88)4218f12This Manual: http://www.manuallib.com/file/2586955LTC4218APPLICATIONS INFORMATION
LTC4218-12VDDOVRSHUNT2
R110ΩSENSE–SENSE+RSHUNT1
4218 F0412VRS2mΩQ1Si7108DN+CL330μFVOUT12V6AUVGATESOURCE12VRGATE1kCGATE0.01μFVDDUVLTC4218DHC-12FLTPGR210kFigure 4. Adjusting LTC4218-12 ThresholdsIn this same fi gure the OV threshold is lowered from 15.05V to 13.5V. Decreasing the OV threshold requires adding a resistor between VDD and OV. This resistor can be calculated as follows:RSHUNT2=
R(IN)•VOLD
V(TH)⎛V–V
⎜NEWOV(TH)⎜(VOLD–VNEW)⎜⎝
CT0.1μFC10.1μFTIMERINTVCCGNDIMONR320k4218 F05ADCFigure 5. 6A, 12V Card Resident Application()⎞⎟=⎟⎟⎠
Calculate the time it takes to charge up COUT: tCHARGUP=
CL•VIN330µF•12V
==4ms
1AIINRUSH
18k•15.05⎛(13.5–1.235)⎞
=1.736M⎟1.235⎜15.05–13.5)⎠⎝(The inrush current is set to 1A using CGATE:CGATE=CL
IGATE(UP)IINRUSH
=330µF
24µA
≅0.01µF1A
Use the equation for RSHUNT1 for increasing the OV and FB thresholds. Likewise, use the equation for RSHUNT2 for decreasing the UV and FB thresholds.Design ExampleConsider the following design example (Figure 5): VIN = 12V, IMAX = 7.5A. IINRUSH = 1A, CL = 330μF, VUVON = 9.88V, VOVOFF = 15.05V, VPWRGD = 10.5V. A current limit fault triggers an automatic restart of the power up sequence.The selection of the sense resistor, (RS), is set by the overcurrent threshold of 15mV: RS = 15mV/IMAX = 15mV/7.5A = 0.002ΩThe MOSFET should be sized to handle the power dissi-pation during the inrush charging of the output capacitor COUT. The method used to determine the power in Q1 is the principal: EC = Energy in CL = Energy in Q1Thus: EC = ½ CV2 = ½ (330μF)(12)2 = 0.048J The average power dissipated in the MOSFET: PDISS = EC/tCHARGUP = 0.048J/4ms = 12WThe SOA (safe operating area) curves of candidate MOSFETs must be evaluated to ensure that the heat capacity of the package can stand 12W for 4ms. The SOA curves of the Vishay Siliconix Si7108DN provide 1.5A at 10V (15W) for 100ms, satisfying the requirement.Next, the power dissipated in the MOSFET during overcurrent must be limited. The active current limit uses a timer to prevent excessive energy dissipation in the MOSFET. The worst-case power occurs when the voltage versus current profi le of the foldback current limit is at the maximum. This occurs when the current is 6A and the voltage is one half of 12V or (6V). See the Current Limit Sense Voltage vs FB Voltage in the Typical Performance curves to view this profi le. In order to survive 36W, the MOSFET SOA dictates a maximum time at this power level. The Si7108DN allows 60W for 10ms or less. Therefore, it is acceptable to set the current limit timeout using CT to be 1.2ms: CT = 1.2ms/12[ms/μF] = 0.1μF4218f13This Manual: http://www.manuallib.com/file/2586955LTC4218APPLICATIONS INFORMATION
After the 1.2ms timeout the FLT pin needs to pull down on the UV pin to restart the power-up sequence.Since the default values for overvoltage, undervoltage and powergood thresholds for the 12V fi xed version match the requirements, no external components are required for the UV, OV and FB pins.The fi nal schematic results in very few external com-ponents. Resistor R1 (10Ω) prevents high frequency oscillations in Q1 while RGATE of 1k isolates CGATE during fast turn-off. The pull-up resistor, (R2), connects to the PG pin while the 20k (R3) converts the IMON current to a voltage at a ratio: VIMON=
6.67µA2mV0.267V
••20k=mVAA
In Hot Swap applications where load currents can be 6A, narrow PCB tracks exhibit more resistances than wider tracks and operate at elevated temperatures. The minimum trace width for 1oz copper foil is 0.02” per amp to make sure the trace stays at a reasonable temperature. Using 0.03” per amp or wider is recommended. Note that 1oz copper exhibits a sheet resistance of about 0.5mΩ/square. Small resistances add up quickly in high current applicationsIt is also important to put C1, the bypass capacitor for the INTVCC pin, as close as possible between the INTVCC and GND. Place the 10Ω resistor as close as possible to Q1. This will limit the parasitic trace capacitance that leads to Q1 self-oscillation.Additional ApplicationsThe LTC4218 has a wide operating range from 2.9V to 26.5V. The UV, OV and PG thresholds are set with a few resistors. All other functions are independent of supply voltage.The last page includes a 24V application with a UV threshold of 19.8V, an OV threshold of 28.3V and a PG threshold of 20.75V. Figure 7 shows a 3.3V application with a UV threshold of 2.87V, an OV threshold of 3.77V and a PG threshold of 3.05V.In addition, there is a 0.1μF bypass (C1) on the INTVCC pin.Layout ConsiderationsTo achieve accurate current sensing, a Kelvin connection for the sense resistor is recommended. The PCB layout should be balanced and symmetrical to minimize wiring errors. In addition, the PCB layout for the sense resistors and the power MOSFETs should include good thermal management techniques for optimal device power dissipa-tion. A recommended PCB layout for the sense resistor and power MOSFET is illustrated in Figure 6.RSQ1RS2mΩ3.3VQ1Si7104DNR110ΩR514.7kRGATE1k+VOUT3.3V6ACL330μF
R1R217.4kSENSE–GATESOURCESENSEVDDUVFLTOVPGCT0.1μFC10.1μF4218 F06+CGATE0.01μFR610kFBLTC4218GN3.3VR710kLTC4218R33.16kR410kTIMERINTVCCGNDIOUTRMON20k4218 F07CADCFigure 6. Recommended LayoutFigure 7. 3.3V, 6A Card Resident Application4218f14This Manual: http://www.manuallib.com/file/2586955LTC4218PACKAGE DESCRIPTION
DHC Package16-Lead Plastic DFN (5mm × 3mm)(Reference LTC DWG # 05-08-1706)5.00 ±0.10(2 SIDES)0.65 ±0.053.00 ±0.10(2 SIDES)PACKAGEOUTLINE1.65 ± 0.10(2 SIDES)PIN 1NOTCH (DHC16) DFN 1103R = 0.115TYPR = 0.20TYP9160.40 ± 0.103.50 ±0.051.65 ±0.05(2 SIDES)2.20 ±0.05PIN 1TOP MARK(SEE NOTE 6)80.200 REF0.75 ±0.054.40 ±0.10(2 SIDES)BOTTOM VIEW—EXPOSED PAD
10.25 ± 0.050.50 BSC0.25 ± 0.050.50 BSC4.40 ±0.05(2 SIDES)RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
0.00 – 0.05NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJED-1) IN JEDECPACKAGE OUTLINE MO-2292. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
GN Package16-Lead Plastic SSOP (Narrow .150 Inch)(Reference LTC DWG # 05-08-1641).045 ±.005 .189 – .196*(4.801 – 4.978)161514131211109.009(0.229)REF.254 MIN.150 – .165.229 – .244(5.817 – 6.198) .150 – .157**(3.810 – 3.988).0165 ±.0015.0250 BSCRECOMMENDED SOLDER PAD LAYOUT
1 .015 ± .004× 45°
(0.38 ± 0.10).007 – .0098(0.178 – 0.249).016 – .050(0.406 – 1.270)NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006\" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010\" (0.254mm) PER SIDE
.0532 – .0688(1.35 – 1.75)2345678.004 – .0098(0.102 – 0.249)0° – 8° TYP.008 – .012(0.203 – 0.305)TYP.0250(0.635)BSC
GN16 (SSOP) 02044218fInformation furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.15This Manual: http://www.manuallib.com/file/2586955LTC4218TYPICAL APPLICATION
24V, 6A Card Resident Application24V
*10Ω1kSENSE–SENSE+215kVDDUV4.32k10kTIMER0.1μF0.1μF*DIODES INC., SMAJ24AINTVCCGNDIMON20k4218 TA022mΩSi7880ADPVOUT24V6A158k+330μFGATESOURCEFB0.01μFFLTOVLTC4218GN24V10kPG10kADCRELATED PARTS
PART NUMBERLTC1421LTC1422LTC1642ALTC1645LTC1647-1/LTC1647-2/LTC1647-3LTC4210LTC4211LTC4212LTC4214LTC4215LT4220LTC4221LTC4230LTC4245DESCRIPTIONDual Channel, Hot Swap ControllerSingle Channel, Hot Swap ControllerSingle Channel, Hot Swap ControllerDual Channel, Hot Swap ControllerDual Channel, Hot Swap ControllersSingle Channel, Hot Swap ControllerSingle Channel, Hot Swap ControllerSingle Channel, Hot Swap ControllerNegative Voltage, Hot Swap ControllerSingle Hot Swap Controller with ADC and I2C InterfacePositive and Negative Voltage, Dual Channel, Hot Swap ControllerDual Hot Swap Controller/SequencerTriple Channel, Hot Swap ControllerCOMMENTSOperates from 3V to 12V, Supports –12V, SSOP-24Operates from 2.7V to 12V, SO-8Operates from 3V to 16.5V, Overvoltage Protection up to 33V, SSOP-16Operates from 3V to 12V, Power Sequencing, SO-8 or SO-14Operates from 2.7V to 16.5V, SO-8 or SSOP-16Operates from 2.7V to 16.5V, Active Current Limiting, SOT23-6Operates from 2.5V to 16.5V, Multifunction Current Control, MSOP-8 or MSOP-10Operates from 2.5V to 16.5V, Power-Up Timeout, MSOP-10Operates from –6V to –16V, MSOP-10Operates from 2.9V to 15V, Digitally Monitors Voltage and Current with 8-Bit ADCOperates from ±2.7V to ±16.5V, SSOP-16Operates from 1V to 13.5V, Multifunction Current Control, SSOP-16Operates from 1.7V to 16.5V, Multifunction Current Control, SSOP-20Quad Hot Swap Controller with ADC and 3.3V, 5V and ±12V for CompactPCI, or 3.3V, 3.3V Auxillary and 12V for PCI-Express, Monitors Voltage and Current with 8-Bit ADCI2C Interface4218f16Linear Technology CorporationLT 0108 • PRINTED IN USA1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com© LINEAR TECHNOLOGY CORPORATION 2007This Manual: http://www.manuallib.com/file/2586955
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