专利名称：SYSTEMS AND METHODS FOR IMPROVING
DIGITAL SYSTEM SIMULATION SPEED BYCLOCK PHASE GATING
发明人：Tauseef Kazi,Haobo Yu,Lukai Cai,Mahesh
Sridharan,Viraphol Chaiyakul
申请号：US12265661申请日：20081105
公开号：US20100114551A1公开日：20100506
专利附图：
摘要：An apparatus for simulating digital systems is described. The apparatus includes
a processor and memory in electronic communication with the processor. Instructionsthat are executable by the processor are stored in the memory. A simulation tool isstarted. The simulation tool is capable of simulating a plurality of components. A clockphase is adjusted to be turned off for at least one of the components. A digital system issimulated that includes the at least one component. The simulation does not simulatethe clock phase for the at least one component.
申请人：Tauseef Kazi,Haobo Yu,Lukai Cai,Mahesh Sridharan,Viraphol Chaiyakul
地址：San Diego CA US,Irvine CA US,San Diego CA US,San Diego CA US,San Diego CA US
国籍：US,US,US,US,US
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